treewide: fix replace nbd@openwrt.org with nbd@nbd.name
[openwrt.org/openwrt.git] / target / linux / ramips / patches-4.4 / 0505-net-next-mediatek-add-support-for-rt2880.patch
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
From f8c8f4bd2a13e0cc060c93812377373d436f7f02 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Wed, 18 Nov 2015 03:13:05 +0100
Subject: [PATCH 505/513] net-next: mediatek: add support for rt2880
 
rt2880 is the oldest SoC with this core. It has a single gBit port that will
normally be attached to an external phy of switch. The patch also adds the
code required to drive the mdio bus.
 
Signed-off-by: John Crispin <blogic@openwrt.org>
Signed-off-by: Felix Fietkau <nbd@nbd.name>
Signed-off-by: Michael Lee <igvtee@gmail.com>
---
 drivers/net/ethernet/mediatek/mdio_rt2880.c |  222 +++++++++++++++++++++++++++
 drivers/net/ethernet/mediatek/mdio_rt2880.h |   23 +++
 drivers/net/ethernet/mediatek/soc_rt2880.c  |   76 +++++++++
 3 files changed, 321 insertions(+)
 create mode 100644 drivers/net/ethernet/mediatek/mdio_rt2880.c
 create mode 100644 drivers/net/ethernet/mediatek/mdio_rt2880.h
 create mode 100644 drivers/net/ethernet/mediatek/soc_rt2880.c
 
--- /dev/null
+++ b/drivers/net/ethernet/mediatek/mdio_rt2880.c
@@ -0,0 +1,222 @@
+/*   This program is free software; you can redistribute it and/or modify
+ *   it under the terms of the GNU General Public License as published by
+ *   the Free Software Foundation; version 2 of the License
+ *
+ *   This program is distributed in the hope that it will be useful,
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *   GNU General Public License for more details.
+ *
+ *   Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
+ *   Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
+ *   Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/of_net.h>
+#include <linux/of_mdio.h>
+
+#include "mtk_eth_soc.h"
+#include "mdio_rt2880.h"
+#include "mdio.h"
+
+#define FE_MDIO_RETRY  1000
+
+static unsigned char *rt2880_speed_str(struct fe_priv *priv)
+{
+       switch (priv->phy->speed[0]) {
+       case SPEED_1000:
+               return "1000";
+       case SPEED_100:
+               return "100";
+       case SPEED_10:
+               return "10";
+       }
+
+       return "?";
+}
+
+void rt2880_mdio_link_adjust(struct fe_priv *priv, int port)
+{
+       u32 mdio_cfg;
+
+       if (!priv->link[0]) {
+               netif_carrier_off(priv->netdev);
+               netdev_info(priv->netdev, "link down\n");
+               return;
+       }
+
+       mdio_cfg = FE_MDIO_CFG_TX_CLK_SKEW_200 |
+                  FE_MDIO_CFG_RX_CLK_SKEW_200 |
+                  FE_MDIO_CFG_GP1_FRC_EN;
+
+       if (priv->phy->duplex[0] == DUPLEX_FULL)
+               mdio_cfg |= FE_MDIO_CFG_GP1_DUPLEX;
+
+       if (priv->phy->tx_fc[0])
+               mdio_cfg |= FE_MDIO_CFG_GP1_FC_TX;
+
+       if (priv->phy->rx_fc[0])
+               mdio_cfg |= FE_MDIO_CFG_GP1_FC_RX;
+
+       switch (priv->phy->speed[0]) {
+       case SPEED_10:
+               mdio_cfg |= FE_MDIO_CFG_GP1_SPEED_10;
+               break;
+       case SPEED_100:
+               mdio_cfg |= FE_MDIO_CFG_GP1_SPEED_100;
+               break;
+       case SPEED_1000:
+               mdio_cfg |= FE_MDIO_CFG_GP1_SPEED_1000;
+               break;
+       default:
+               BUG();
+       }
+
+       fe_w32(mdio_cfg, FE_MDIO_CFG);
+
+       netif_carrier_on(priv->netdev);
+       netdev_info(priv->netdev, "link up (%sMbps/%s duplex)\n",
+                   rt2880_speed_str(priv),
+                   (priv->phy->duplex[0] == DUPLEX_FULL) ? "Full" : "Half");
+}
+
+static int rt2880_mdio_wait_ready(struct fe_priv *priv)
+{
+       int retries;
+
+       retries = FE_MDIO_RETRY;
+       while (1) {
+               u32 t;
+
+               t = fe_r32(FE_MDIO_ACCESS);
+               if ((t & BIT(31)) == 0)
+                       return 0;
+
+               if (retries-- == 0)
+                       break;
+
+               udelay(1);
+       }
+
+       dev_err(priv->device, "MDIO operation timed out\n");
+       return -ETIMEDOUT;
+}
+
+int rt2880_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg)
+{
+       struct fe_priv *priv = bus->priv;
+       int err;
+       u32 t;
+
+       err = rt2880_mdio_wait_ready(priv);
+       if (err)
+               return 0xffff;
+
+       t = (phy_addr << 24) | (phy_reg << 16);
+       fe_w32(t, FE_MDIO_ACCESS);
+       t |= BIT(31);
+       fe_w32(t, FE_MDIO_ACCESS);
+
+       err = rt2880_mdio_wait_ready(priv);
+       if (err)
+               return 0xffff;
+
+       pr_debug("%s: addr=%04x, reg=%04x, value=%04x\n", __func__,
+                phy_addr, phy_reg, fe_r32(FE_MDIO_ACCESS) & 0xffff);
+
+       return fe_r32(FE_MDIO_ACCESS) & 0xffff;
+}
+
+int rt2880_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val)
+{
+       struct fe_priv *priv = bus->priv;
+       int err;
+       u32 t;
+
+       pr_debug("%s: addr=%04x, reg=%04x, value=%04x\n", __func__,
+                phy_addr, phy_reg, fe_r32(FE_MDIO_ACCESS) & 0xffff);
+
+       err = rt2880_mdio_wait_ready(priv);
+       if (err)
+               return err;
+
+       t = (1 << 30) | (phy_addr << 24) | (phy_reg << 16) | val;
+       fe_w32(t, FE_MDIO_ACCESS);
+       t |= BIT(31);
+       fe_w32(t, FE_MDIO_ACCESS);
+
+       return rt2880_mdio_wait_ready(priv);
+}
+
+void rt2880_port_init(struct fe_priv *priv, struct device_node *np)
+{
+       const __be32 *id = of_get_property(np, "reg", NULL);
+       const __be32 *link;
+       int size;
+       int phy_mode;
+
+       if (!id || (be32_to_cpu(*id) != 0)) {
+               pr_err("%s: invalid port id\n", np->name);
+               return;
+       }
+
+       priv->phy->phy_fixed[0] = of_get_property(np,
+                                                 "mediatek,fixed-link", &size);
+       if (priv->phy->phy_fixed[0] &&
+           (size != (4 * sizeof(*priv->phy->phy_fixed[0])))) {
+               pr_err("%s: invalid fixed link property\n", np->name);
+               priv->phy->phy_fixed[0] = NULL;
+               return;
+       }
+
+       phy_mode = of_get_phy_mode(np);
+       switch (phy_mode) {
+       case PHY_INTERFACE_MODE_RGMII:
+               break;
+       case PHY_INTERFACE_MODE_MII:
+               break;
+       case PHY_INTERFACE_MODE_RMII:
+               break;
+       default:
+               if (!priv->phy->phy_fixed[0])
+                       dev_err(priv->device, "port %d - invalid phy mode\n",
+                               priv->phy->speed[0]);
+               break;
+       }
+
+       priv->phy->phy_node[0] = of_parse_phandle(np, "phy-handle", 0);
+       if (!priv->phy->phy_node[0] && !priv->phy->phy_fixed[0])
+               return;
+
+       if (priv->phy->phy_fixed[0]) {
+               link = priv->phy->phy_fixed[0];
+               priv->phy->speed[0] = be32_to_cpup(link++);
+               priv->phy->duplex[0] = be32_to_cpup(link++);
+               priv->phy->tx_fc[0] = be32_to_cpup(link++);
+               priv->phy->rx_fc[0] = be32_to_cpup(link++);
+
+               priv->link[0] = 1;
+               switch (priv->phy->speed[0]) {
+               case SPEED_10:
+                       break;
+               case SPEED_100:
+                       break;
+               case SPEED_1000:
+                       break;
+               default:
+                       dev_err(priv->device, "invalid link speed: %d\n",
+                               priv->phy->speed[0]);
+                       priv->phy->phy_fixed[0] = 0;
+                       return;
+               }
+               dev_info(priv->device, "using fixed link parameters\n");
+               rt2880_mdio_link_adjust(priv, 0);
+               return;
+       }
+
+       if (priv->phy->phy_node[0] && priv->mii_bus->phy_map[0])
+               fe_connect_phy_node(priv, priv->phy->phy_node[0]);
+}
--- /dev/null
+++ b/drivers/net/ethernet/mediatek/mdio_rt2880.h
@@ -0,0 +1,23 @@
+/*   This program is free software; you can redistribute it and/or modify
+ *   it under the terms of the GNU General Public License as published by
+ *   the Free Software Foundation; version 2 of the License
+ *
+ *   This program is distributed in the hope that it will be useful,
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *   GNU General Public License for more details.
+ *
+ *   Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
+ *   Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
+ *   Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
+ */
+
+#ifndef _RALINK_MDIO_RT2880_H__
+#define _RALINK_MDIO_RT2880_H__
+
+void rt2880_mdio_link_adjust(struct fe_priv *priv, int port);
+int rt2880_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg);
+int rt2880_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val);
+void rt2880_port_init(struct fe_priv *priv, struct device_node *np);
+
+#endif
--- /dev/null
+++ b/drivers/net/ethernet/mediatek/soc_rt2880.c
@@ -0,0 +1,76 @@
+/*   This program is free software; you can redistribute it and/or modify
+ *   it under the terms of the GNU General Public License as published by
+ *   the Free Software Foundation; version 2 of the License
+ *
+ *   This program is distributed in the hope that it will be useful,
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *   GNU General Public License for more details.
+ *
+ *   Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
+ *   Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
+ *   Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
+ */
+
+#include <linux/module.h>
+
+#include <asm/mach-ralink/ralink_regs.h>
+
+#include "mtk_eth_soc.h"
+#include "mdio_rt2880.h"
+
+#define RT2880_RESET_FE                        BIT(18)
+
+static void rt2880_init_data(struct fe_soc_data *data,
+                            struct net_device *netdev)
+{
+       struct fe_priv *priv = netdev_priv(netdev);
+
+       priv->flags = FE_FLAG_PADDING_64B | FE_FLAG_PADDING_BUG |
+               FE_FLAG_JUMBO_FRAME | FE_FLAG_CALIBRATE_CLK;
+       netdev->hw_features = NETIF_F_SG | NETIF_F_HW_VLAN_CTAG_TX;
+       /* this should work according to the datasheet but actually does not*/
+       /* netdev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_RXCSUM; */
+}
+
+void rt2880_fe_reset(void)
+{
+       fe_reset(RT2880_RESET_FE);
+}
+
+static int rt2880_fwd_config(struct fe_priv *priv)
+{
+       int ret;
+
+       ret = fe_set_clock_cycle(priv);
+       if (ret)
+               return ret;
+
+       fe_fwd_config(priv);
+       fe_w32(FE_PSE_FQFC_CFG_INIT, FE_PSE_FQ_CFG);
+       fe_csum_config(priv);
+
+       return ret;
+}
+
+struct fe_soc_data rt2880_data = {
+       .init_data = rt2880_init_data,
+       .reset_fe = rt2880_fe_reset,
+       .fwd_config = rt2880_fwd_config,
+       .pdma_glo_cfg = FE_PDMA_SIZE_8DWORDS,
+       .checksum_bit = RX_DMA_L4VALID,
+       .rx_int = FE_RX_DONE_INT,
+       .tx_int = FE_TX_DONE_INT,
+       .status_int = FE_CNT_GDM_AF,
+       .mdio_read = rt2880_mdio_read,
+       .mdio_write = rt2880_mdio_write,
+       .mdio_adjust_link = rt2880_mdio_link_adjust,
+       .port_init = rt2880_port_init,
+};
+
+const struct of_device_id of_fe_match[] = {
+       { .compatible = "ralink,rt2880-eth", .data = &rt2880_data },
+       {},
+};
+
+MODULE_DEVICE_TABLE(of, of_fe_match);
 
comments