Merge branch 'master' of git://nbd.name/openwrt
[openwrt.git] / package / kernel / mac80211 / patches / 566-ath9k-ar933x-usb-hang-workaround.patch
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--- a/drivers/net/wireless/ath/ath9k/hw.c
+++ b/drivers/net/wireless/ath/ath9k/hw.c
@@ -217,6 +217,19 @@ void ath9k_hw_get_channel_centers(struct
                centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
 }
 
+static inline void ath9k_hw_disable_pll_lock_detect(struct ath_hw *ah)
+{
+       /* On AR9330 and AR9340 devices, some PHY registers must be
+        * tuned to gain better stability/performance. These registers
+        * might be changed while doing wlan reset so the registers must
+        * be reprogrammed after each reset.
+        */
+       REG_CLR_BIT(ah, AR_PHY_USB_CTRL1, BIT(20));
+       REG_RMW(ah, AR_PHY_USB_CTRL2,
+               (1 << 21) | (0xf << 22),
+               (1 << 21) | (0x3 << 22));
+}
+
 /******************/
 /* Chip Revisions */
 /******************/
@@ -1337,6 +1350,9 @@ static bool ath9k_hw_set_reset(struct at
        if (AR_SREV_9100(ah))
                udelay(50);
 
+       if (AR_SREV_9330(ah) || AR_SREV_9340(ah))
+               ath9k_hw_disable_pll_lock_detect(ah);
+
        return true;
 }
 
@@ -1436,6 +1452,9 @@ static bool ath9k_hw_chip_reset(struct a
                ar9003_hw_internal_regulator_apply(ah);
        ath9k_hw_init_pll(ah, chan);
 
+       if (AR_SREV_9330(ah) || AR_SREV_9340(ah))
+               ath9k_hw_disable_pll_lock_detect(ah);
+
        return true;
 }
 
@@ -1730,8 +1749,14 @@ static int ath9k_hw_do_fastcc(struct ath
        if (AR_SREV_9271(ah))
                ar9002_hw_load_ani_reg(ah, chan);
 
+       if (AR_SREV_9330(ah) || AR_SREV_9340(ah))
+               ath9k_hw_disable_pll_lock_detect(ah);
+
        return 0;
 fail:
+       if (AR_SREV_9330(ah) || AR_SREV_9340(ah))
+               ath9k_hw_disable_pll_lock_detect(ah);
+
        return -EINVAL;
 }
 
@@ -1959,6 +1984,9 @@ int ath9k_hw_reset(struct ath_hw *ah, st
        if (AR_SREV_9565(ah) && common->bt_ant_diversity)
                REG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV, AR_BTCOEX_WL_LNADIV_FORCE_ON);
 
+       if (AR_SREV_9330(ah) || AR_SREV_9340(ah))
+               ath9k_hw_disable_pll_lock_detect(ah);
+
        return 0;
 }
 EXPORT_SYMBOL(ath9k_hw_reset);
--- a/drivers/net/wireless/ath/ath9k/phy.h
+++ b/drivers/net/wireless/ath/ath9k/phy.h
@@ -48,6 +48,9 @@
 #define AR_PHY_PLL_CONTROL 0x16180
 #define AR_PHY_PLL_MODE 0x16184
 
+#define AR_PHY_USB_CTRL1       0x16c84
+#define AR_PHY_USB_CTRL2       0x16c88
+
 enum ath9k_ant_div_comb_lna_conf {
        ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2,
        ATH_ANT_DIV_COMB_LNA2,
 
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